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document # sram119 rev i revised july 2010 p4c1256 high speed 32k x 8 static cmos ram features high speed (equal access and cycle times) C 12/15/20/25/35 ns (commercial) C 15/20/25/35/45 ns (industrial) C 20/25/35/45/55/70 ns (military) low power single 5v10% power supply easy memory expansion using ce and oe inputs common data i/o three-state outputs fully ttl compatible inputs and outputs advanced cmos technology fast t oe automatic power down packages C 28-pin 300 mil dip, soj, tsop C 28-pin 300 mil ceramic dip C 28-pin 600 mil plastic and ceramic dip C 28-pin cerpack C 28-pin solder seal flat pack C 28-pin sop C 28-pin lcc (350 mil x 550 mil) C 32-pin lcc (450 mil x 550 mil) functional block diagram pin config urations lcc and tsop confgurations at end of datasheet dip (p5, p6, c5, c5-1, d5-1, d5-2), soj (j5), sop (s11-1, s11-3) cerpack (f4, fs-5) similar description the p4c1256 is a 262,144-bit high-speed cmos static ram organized as 32k x 8. the cmos memory requires no clocks or refreshing, and has equal access and cycle times. inputs are fully ttl-compatible. the ram operates from a single 5v10% tolerance power supply. access times as fast as 12 nanoseconds permit greatly enhanced system operating speeds. cmos is utilized to reduce power consumption to a low level. the p4c1256 is a member of a family of pace ram? products offering fast access times. the p4c1256 devices provides asynchronous operation with matching access and cycle times. memory locations are specifed on address pins a 0 to a 14 . reading is accom - plished by device selection ( ce ) and output enabling ( oe ) while write enable ( we ) remains high. by presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. the input/output pins stay in the high z state when either ce or oe is high or we is low. package options for the p4c1256 include 28-pin dip, soj, and tsop packages. for military temperature range, ceramic dip and lcc packages are available.
p4c1256 - high speed 32k x 8 static cmos ram page 2 document # sram119 rev i dc electrical characteristics (over recommended operating temperature & supply voltage) (2) sym parameter value unit v cc power supply pin with respect to gnd -0.5 to +7 v v term terminal voltage with respect to gnd (up to 7.0v) -0.5 to vcc + 0.5 v t a operating temperature -55 to +125 c t bias temperature under bias -55 to +125 c t stg storage temperature -65 to +150 c p t power dissipation 1.0 w i out dc output current 50 ma maximum r atings (1) recommen ded operating conditions grade (2) ambient temp gnd v cc commercial 0c to 70c 0v 5.0v 10% industrial -40c to +85c 0v 5.0v 10% military -55c to +125c 0v 5.0v 10% capacita nces (4) (v cc = 5.0v, t a = 25c, f = 1.0mhz) sym parameter conditions typ unit c in input capacitance v in =0v 8 pf c out output capacitance v out =0v 10 pf sym parameter test conditions p4c1256 p4c1256l unit min max min max v ih input high voltage 2.2 v cc + 0.5 2.2 v cc + 0.5 v v il input low voltage -0.5 (3) 0.8 -0.5 (3) 0.8 v v hc cmos input high voltage v cc - 0.2 v cc + 0.5 v cc - 0.2 v cc + 0.5 v v lc cmos input low voltage -0.5 (3) 0.2 -0.5 (3) 0.2 v v ol output low voltage (ttl load) i ol = +8 ma, v cc = min 0.4 0.4 v v oh output high voltage (ttl load) i oh = - 4 ma, v cc = min 2.4 2.4 v i li input leakage current v cc = max, v in = gnd to v cc mil -10 +10 -5 +5 a ind/com -5 +5 n/a n/a i lo output leakage current v cc = max, ce = v ih , v out = gnd to v cc mil -10 +10 -5 +5 a ind/com -5 +5 n/a n/a i sb standby power supply current (ttl input levels) ce v ih , v cc = max, f = max, outputs open mil 45 30 ma ind/com 30 n/a i sb1 standby power supply current (cmos input levels) ce v hc , v cc = max, f = 0, outputs open v in v lc or v in v hc mil 20 10 ma ind/com 10 n/a n/a = not applicable
p4c1256 - high speed 32k x 8 static cmos ram page 3 document # sram119 rev i data rete ntion characteristics (p4c1256l military temperature only) data rete ntion waveform sym parameter test conditions min typ* v cc = max v cc = unit 2.0v 3.0v 2.0v 3.0v v dr v cc for data retention 2.0 v i ccdr data retention current ce v cc -0.2v, v in v cc -0.2v or v in 0.2v 10 15 100 200 a t cdr chip deselect to data retention time 0 ns t r ? operation recovery time t rc ns * t a = +25c t rc = read cycle time ? this parameter is guaranteed but not tested power dissipatio n characteristics vs. speed sym parameter temperature range -12 -15 -20 -25 -35 -45 -55 -70 unit i cc dynamic operating current* commercial 170 160 155 150 145 n/a n/a n/a ma industrial n/a 170 165 160 155 150 n/a n/a ma military n/a n/a 170 165 160 155 150 150 ma * v cc = 5.5v. tested with outputs open. f = max. switching inputs are 0v and 3v. ce = v il , oe = v ih . sym parameter -12 -15 -20 -25 -35 -45 -55 -70 unit min max min max min max min max min max min max min max min max t rc read cycle time 12 15 20 25 35 45 55 70 ns t aa address access time 12 15 20 25 35 45 55 70 ns t ac chip enable access time 12 15 20 25 35 45 55 70 ns t oh output hold from address change 2 2 2 3 3 3 3 3 ns t lz chip enable to output in low z 2 2 2 3 3 3 3 3 ns t hz chip disable to output in high z 5 8 9 11 15 20 25 30 ns t oe output enable low to data valid 5 7 9 10 15 20 25 30 ns t olz output enable low to low z 0 0 0 0 0 0 0 0 ns t ohz output enable high to high z 5 7 9 11 15 20 25 30 ns t pu chip enable to power up time 0 0 0 0 0 0 0 0 ns t pd chip disable to power down time 12 15 20 20 20 25 30 35 ns ac electrical characteristicsread cycle (v cc = 5v 10%, all temperature ranges) (2)
p4c1256 - high speed 32k x 8 static cmos ram page 4 document # sram119 rev i timing waveform of read cycle no. 1 ( oe controlled) (5) timing waveform of read cycle no. 2 (address controlled) (5,6) timing waveform of read cycle no. 3 ( ce controlled) notes: 1. stresses greater than those listed under maximum r atings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to maximum rating conditions for extended periods may affect reliability. 2. extended temperature operation guaranteed with 400 linear feet per minute of air fow. 3. transient inputs with v il and i il not more negative than C3.0v and C100ma, respectively, are permissible for pulse widths up to 20 ns. 4. this parameter is sampled and not 100% tested. 5. we is high for read cycle. 6. ce is low and oe is low for read cycle. 7. address must be valid prior to, or coincident with ce transition low. 8. transition is measured 200 mv from steady state voltage prior to change, with loading as specifed in figure 1. this parameter is sampled and not 100% tested. 9. read cycle time is measured from the last valid address to the frst transitioning address.
p4c1256 - high speed 32k x 8 static cmos ram page 5 document # sram119 rev i ac characteristicswrite cycle (v cc = 5v 10%, all temperature ranges) (2) sym parameter -12 -15 -20 -25 -35 -45 -55 -70 unit min max min max min max min max min max min max min max min max t wc write cycle time 12 15 20 25 35 45 55 70 ns t cw chip enable time to end of write 9 10 15 18 22 30 35 40 ns t aw address valid to end of write 9 10 15 20 25 35 40 45 ns t as address setup time 0 0 0 0 0 0 0 0 ns t wp write pulse width 9 11 15 18 22 25 30 35 ns t ah address hold time 0 0 0 0 0 0 0 0 ns t dw data valid to end of write 8 9 11 13 15 20 25 30 ns t dh data hold time 0 0 0 0 0 0 0 0 ns t wz write enable to output in high z 7 8 10 11 15 18 25 30 ns t ow output active from end of write 3 3 3 3 3 3 3 3 ns timing waveform of write cycle no. 1 ( we controlled) (10,11) notes: 10. ce and we must be low for write cycle. 11. oe is low for this write cycle to show t wz and t ow . 12. if ce goes high simultaneously with we high, the output remains in a high impedance state 13. write cycle time is measured from the last valid address to the frst transitioning address.
p4c1256 - high speed 32k x 8 static cmos ram page 6 document # sram119 rev i ac test conditions truth table timing w aveform of write cycle no. 2 ( ce controlled) (10) input pulse levels gnd to 3.0v input rise and fall times 3ns input timing reference level 1.5v output timing reference level 1.5v output load see figures 1 and 2 mode ce oe we i/o power standby h x x high z standby d out disabled l h h high z active read l l h d out active write l x l high z active figure 1. output load figure 2. thevenin equivalent * including scope and test fxture. note: because of the ultra-high speed of the p4c1256, care must be taken when testing this device; an inadequate setup can cause a normal function - ing part to be rejected as faulty. long high-inductance leads that cause supply bounce must be avoided by bringing the v cc and ground planes directly up to the contactor fngers. a 0.01 f high frequency capacitor is also required between v cc and ground. to avoid signal refections, proper termination must be used; for example, a 50? test environment should be terminated into a 50? load with 1.73v (thevenin voltage) at the comparator input, and a 116? resistor must be used in series with d out to match 166? (thevenin resistance).
p4c1256 - high speed 32k x 8 static cmos ram page 7 document # sram119 rev i ordering in formation
p4c1256 - high speed 32k x 8 static cmos ram page 8 document # sram119 rev i 28-pin lcc (l5) 32-pin lcc (l6) lcc pin config urations tsop (t1)
p4c1256 - high speed 32k x 8 static cmos ram page 9 document # sram119 rev i side brazed ceramic dual i n-lin e package (300 mils) pkg # c5 # pins 28 (300 mil) symbol min max a - 0.225 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d - 1.485 e 0.240 0.310 ea 0.300 bsc e 0.100 bsc l 0.125 0.200 q 0.015 0.070 s1 0.005 - s2 0.005 - pkg # c5-1 # pins 28 (600 mil) symbol min max a - 0.232 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d - 1.490 e 0.500 0.610 ea 0.600 bsc e 0.100 bsc l 0.125 0.200 q 0.015 0.060 s1 0.005 - s2 0.005 - side brazed ceramic dual i n-lin e package (600 mils)
p4c1256 - high speed 32k x 8 static cmos ram page 10 document # sram119 rev i cerdip dual i n-lin e package cerdip dual i n-lin e package pkg # d5-1 # pins 28 (600 mil) symbol min max a - 0.232 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d - 1.490 e 0.500 0.610 ea 0.600 bsc e 0.100 bsc l 0.125 0.200 q 0.015 0.060 s1 0.005 - 0 15 pkg # d5-2 # pins 28 (300 mil) symbol min max a - 0.225 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d - 1.485 e 0.240 0.310 ea 0.300 bsc e 0.100 bsc l 0.125 0.200 q 0.015 0.060 s1 0.005 - 0 15
p4c1256 - high speed 32k x 8 static cmos ram page 11 document # sram119 rev i cerpack ceramic flat packa ge pkg # f4 # pins 28 symbol min max a 0.060 0.090 b 0.015 0.022 c 0.004 0.009 d - 0.730 e 0.330 0.380 e 0.050 bsc k 0.005 0.018 l 0.250 0.370 q 0.026 0.045 s - 0.085 s1 0.005 - solder seal flat pack pkg # fs-5 # pins 28 symbol min max a 0.090 0.130 b 0.015 0.022 c 0.004 0.009 d 0.740 e 0.380 0.420 e1 - 0.440 e2 0.180 - e3 0.030 - e 0.050 bsc l 0.250 0.370 q 0.026 0.045 s1 0.000 -
p4c1256 - high speed 32k x 8 static cmos ram page 12 document # sram119 rev i recta ng ular leadless chip carrier (28 pins) pkg # l5 # pins 28 symbol min max a 0.060 0.075 a1 0.050 0.065 b1 0.022 0.028 d 0.342 0.358 d1 0.200 bsc d2 0.100 bsc d3 - 0.358 e 0.540 0.560 e1 0.400 bsc e2 0.200 bsc e3 - 0.558 e 0.050 bsc h 0.040 ref j 0.020 ref l 0.045 0.055 l1 0.045 0.055 l2 0.075 0.095 nd 5 ne 9 soj small outli n e ic package pkg # j5 # pins 28 (300 mil) symbol min max a 0.120 0.148 a1 0.078 - b 0.014 0.020 c 0.007 0.011 d 0.700 0.730 e 0.050 bsc e 0.292 0.300 e1 0.335 0.347 e2 0.262 0.272 q 0.025 -
p4c1256 - high speed 32k x 8 static cmos ram page 13 document # sram119 rev i plastic dual i n-lin e package pkg # p5 # pins 28 (300 mil) symbol min max a - 0.210 a1 - b 0.014 0.023 b2 0.045 0.070 c 0.008 0.014 d 1.345 1.400 e1 0.270 0.300 e 0.300 0.380 e 0.100 bsc eb - 0.430 l 0.115 0.150 0 15 recta ng ular leadless chip carrier (32 pins) pkg # l6 # pins 32 symbol min max a 0.060 0.075 a1 0.050 0.065 b1 0.022 0.028 d 0.442 0.458 d1 0.300 bsc d2 0.150 bsc d3 - 0.458 e 0.540 0.560 e1 0.400 bsc e2 0.200 bsc e3 - 0.558 e 0.050 bsc h 0.040 ref j 0.020 ref l 0.045 0.055 l1 0.045 0.055 l2 0.075 0.095 nd 7 ne 9
p4c1256 - high speed 32k x 8 static cmos ram page 14 document # sram119 rev i pkg # t1 # pins 28 symbol min max a 0.039 0.047 a 2 0.036 0.040 b 0.007 0.011 d 0.461 0.469 e 0.311 0.319 e 0.022 bsc h d 0.520 0.535 tsop thi n small outlin e packacge (8 x 13.4 mm) plastic dual i n-lin e package pkg # p6 # pins 28 (600 mil) symbol min max a 0.090 0.200 a1 0.000 0.070 b 0.014 0.020 b2 0.015 0.065 c 0.008 0.012 d 1.380 1.480 e1 0.485 0.550 e 0.600 0.625 e 0.100 bsc eb 0.600 typ l 0.100 0.200 0 15
p4c1256 - high speed 32k x 8 static cmos ram page 15 document # sram119 rev i soic/sop small outli n e ic package pkg # s11-3 # pins 28 (300 mil) symbol min max a 0.094 0.110 a1 0.002 0.014 b 0.014 0.020 c 0.008 0.012 d 0.702 0.710 e 0.050 bsc e 0.291 0.300 h 0.463 0.477 h 0.010 0.029 l 0.020 0.042 0 8 soic/sop small outli n e ic package pkg # s11-1 # pins 28 (300 mil) symbol min max a 0.093 0.104 a1 0.004 0.012 b2 0.013 0.020 c 0.009 0.012 d 0.696 0.712 e 0.050 bsc e 0.291 0.299 h 0.394 0.419 h 0.010 0.029 l 0.016 0.050 0 8
p4c1256 - high speed 32k x 8 static cmos ram page 16 document # sram119 rev i revisions document number sram 119 document title p4c1256 high speed 32k x 8 static cmos ram rev issue date origin ator description of change or 1997 rkk new data sheet a oct-2005 jdb changed logo to pyramid b oct-2005 jdb added sop package c apr-2006 jdb added lead-free to ordering information d may-2006 jdb added pdip to ordering information e jun-2006 jdb added ceramic dip package f aug-2006 jdb updated soj package information g jun-2007 jdb corrected sop package information h july-2009 jdb added 28-pin 600 mil cerdip, 600 mil pdip. i july 2010 jdb added 28-pin solder seal flat pack

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